1. Field of the Invention
The present invention is related to a fabrication method of a trenched power Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and in particular, to a fabrication method of a trenched power MOSFET with low gate impedance.
2. Description of Related Art
To match the requirements of energy conservation and reduction of the system power loss, higher efficiency of power converting is required. These requirements for design standard which keep pace with the times are the severe challenge to the designer of power converter. Thus, the role of new power device in the high efficiency converter is more important day by day. Wherein, Power MOSFET has been applied widespreadly in various power converters.
FIGS. 1A to 1E show the fabrication process of the conventional trenched power MOSFET. And an N-type power MOSFET is taken as an example.
First, referring to FIG. 1A, an N-type epitaxial layer 120 is formed on the N-type silicon substrate 110. Then, the location of gate trenches 130 is defined by using a mask (not shown). Afterwards, a plurality of gate trenches 130 is formed in the epitaxial layer 120 by undertaking the dry etching process. Thereafter, a gate oxide layer 140 is formed on the exposed surface in the gate trench 130. Afterwards, the N-type epitaxial layer 120 is covered by a polysilicon layer 150 and the gate trenches 130 are completely filled with the polysilicon layer 150.
Then, referring to FIG. 1B, an etching back process is undertaken to remove part of the polysilicon layer 150 which is located above the upper surface of the epitaxial layer 120. And, a plurality of polysilicon gates 152 left in the gate trenches is formed. Later on, referring to FIG. 1C, a blanket ion implantation process is performed to implant P-type dopants into the N-type epitaxial layer 120. Then, the implanted P-type dopants are driven in by undertaking a thermal process, in order to form a P-body 122 in the N-type epitaxial layer 120.
The following step, referring to FIG. 1D, a patterned photoresistant layer 162 is formed by using a mask (not shown), in order to define the location of source regions. Then, the N-type dopants are implanted into the P-body 122 by performing an ion implantation process. Afterwards, the implanted N-type dopants are driven in by undertaking a thermal process, in order to form a plurality of N-type source regions 160 in the P-body 122.
Then, referring to FIG. 1E, a dielectric layer 180 (for example, a BPSG layer) is deposited to cover the polysilicon gates 152, the source regions 160 and the exposed P-body 122. Thereafter, the location of a contact window 182 is defined in the dielectric layer 180 by using a mask (not shown). And the contact window 182 is formed by undertaking the etching process, in order to expose the source regions 160 beneath the dielectric layer 180 and the P-body 122 between the two source regions 160. Later on, through the contact window 182, an ion implantation process is undertaken to implant P-type dopants and a P-type heavily-doped region 190 is formed between the two source regions 160. The fabrication method of trenched power MOSFET is thus completed.
For higher integration, the dimension of MOSFET device becomes smaller. Hence, the width and depth of the gate trench 130 have to become smaller correspondingly. However, the smaller dimension of the gate trench 130 will lead the high resistance of the polysilicon gate 152. This will have a disadvantage to the switching speed of the transistor and also cause the increase of switching loss.
Generally speaking, polysilicon material has high resistivity (usually is bigger than 1 mΩ-cm). In order to reduce resistance of the polysilicon gate 152, a typical fabrication method is performed to form a self-alignment silicide on the polysilicon gate 152. Silicide has lower resistance than polysilicon material; therefore, this is an effective solution to the problem of high gate impedance.
As to the process of self alignment silicide, the formation of silicide has to be delayed after the steps of ion implantation and thermal drive-in, in order to effectively control the thickness of silicide and prevent the pollution causing by diffusion of metal atoms in high-temperature environment. However, referring to FIGS. 1B and 1C, the step of ion drive-in is usually performed in a high-oxygen environment, in order to form a silicon oxide layer 140a on the surface of the epitaxial layer 120, and to prevent the implanted ion from spreading outwards. But, the polysilicon gates 152 in the gate trenches 130 are also exposed. Hence, a silicon oxide layer 140b is formed on the surface of the polysilicon gates 152. In addition, because the polysilicon gates 152 is usually composed of high concentration dopants, the thickness of the silicon oxide layer 140b which is formed on the surface of the polysilicon gates 152 will be even greater than the thickness of the silicon oxide layer 140a which is formed on the surface of the epitaxial layer 120.
It is worth noting that the silicon oxide layer 140a and 140b will hinder the formation of silicide. Therefore, referring to FIG. 1D, in order to form the self alignment silicide (salicide), it is necessary to remove the silicon oxide layer 140b on the surface of the polysilicon gates 152. Meanwhile, the silicon oxide layer 140a on the surface of the epitaxial layer 120 has to be reserved. However, the thickness of the silicon oxide layer 140b on the surface of the polysilicon gates 152 is greater than the thickness of silicon oxide layer 140a on the surface of epitaxial layer 120. Therefore, it is difficult to perform the etching process merely removing the silicon oxide layer 140b on the surface of the polysilicon gates 152 and reserving the silicon oxide layer 140a on the surface of the epitaxial layer 120. As a result, it is difficult to use the silicon oxide layer 140a on the surface of the epitaxial layer 120 as a mask to form silicide on the surface of the polysilicon gates 152.